Method and apparatus for generating generic descrambled data patterns for testing ECC protected memory

ABSTRACT

A method and apparatus for generating bits for a diagnostic routine of a memory subsystem. A memory device may be divided into n subdivisions of m bits each. Alternatively, n memory devices may each have m bits (in width). The system may also have a cache line having a certain number of check words. A diagnostic routine may begin with the generating one of  2   m  bit patterns and assigning m bits of the generated bit pattern to one of the check words in the cache line. Each of the m bits assigned to the check word in the cache line may have the same logic value. However, each bit of the n subdivisions may be associated with a different check word in the cache line with respect to other bits of the subdivision. The method may be repeated for each of the  2   m  bit patterns that may be generated.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] This invention relates to computer systems, and moreparticularly, to diagnostic testing of memory systems.

[0003] 2. Description of the Related Art

[0004] Computers and other electronic systems often undergo diagnosticroutines. Diagnostic routines may be performed to ensure thefunctionality of various devices and interconnections within the system,and may also be used to isolate failing devices.

[0005] Memory subsystems are an integral part of computer system andmany other types of electronic subsystems and are thus subject todiagnostic testing. In testing memory subsystems, it is desirable tohave the ability to detect failures of individual memory devices, suchas an individual DRAM (dynamic random access memory). In order to ensurethat the failure of an individual memory device is detected, it issometime necessary to apply a number of diagnostic patterns to thedevice. For at least some of these patterns, it is desirable that theyinclude both a number of logic 1's and logic 0's.

[0006] Many memory subsystems include an error correction subsystemwhich may implement error correction codes (ECC). An ECC may generateone or more check bits that are associated with a data block. Errorcorrection codes may be used to determine the presence of an error in adata block. Typical ECC subsystems may detect and correct single biterrors in a given memory block (SEC), and may also detect double biterrors in the memory block (DED). Some ECC subsystems may also includethe capability of 4-bit nibble error detection (S4ED). In order toperform these error detection/correction functions, it may be necessarythat bits from a given memory device are routed to different checkwords. In some cases however, the need to route bits from a given memorydevice to different check words may constrain the ability to assign bitsfor diagnostic routines. In particular, such constraints may in somecases result in bit assignments that result in diagnostic patterns whereeach bit assigned to a given memory device has the same logic value.Such diagnostic patterns may be unsatisfactory for detecting a failingmemory device.

SUMMARY OF THE INVENTION

[0007] A method and apparatus for assigning bits for a diagnosticroutine to a memory subsystem is disclosed. In one embodiment, a memorydevice of a computer system may be divided into n subdivisions of m bitseach, while in another embodiment the n memory devices may each have mbits (m is the width of the subdivisions/memory devices). The computersystem may also include a cache memory having a cache line having acertain number of check words. As used herein, the term “check word”refers to a word in a cache line that may include check bits andassociated data bits that are protected by the check bits. Performing adiagnostic routine may begin with the generating one of 2^(m) bitpatterns and assigning m bits of the generated bit patterns to checkwords in the cache line. Each of the m bits assigned to the check wordsin the cache line may have the same logic value. However, each bit ofthe n subdivisions (or n memory devices) may be associated with adifferent check word in the cache line with respect to other bits of thesubdivision (or memory device). Thus, while the logic values of the bitsin each check word of the cache line may be the same, the logic valuesassociated with each memory device or subdivision may be mixed. Themethod may be repeated for each of the 2^(m) bit patterns that may begenerated. Diagnostic tests may be run for each of the generated bitpatterns.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Other aspects of the invention will become apparent upon readingthe following detailed description and upon reference to theaccompanying drawings in which:

[0009]FIG. 1A is a block diagram of one embodiment of a computer system;

[0010]FIG. 1B is a block diagram of one embodiment of a memory module;

[0011]FIG. 2 is a block diagram illustrating one embodiment of a cacheline and a check word associated with the cache line;

[0012]FIG. 3 is a block diagram illustrating the association of checkwords and memory devices; and

[0013]FIG. 4 is a block diagram illustrating various memory devices andpotential subdivisions thereof.

[0014] While the invention is susceptible to various modifications andalternative forms, specific embodiments thereof are shown by way ofexample in the drawings and will herein be described in detail. Itshould be understood, however, that the drawings and description theretoare not intended to limit the invention to the particular formdisclosed, but, on the contrary, the invention is to cover allmodifications, equivalents, and alternatives falling with the spirit andscope of the present invention as defined by the appended claims.

DETAILED DESCRIPTION OF THE INVENTION

[0015] Turning now to FIG. 1A, a block diagram of one embodiment of acomputer system is shown. In the embodiment shown includes centralprocessing unit (CPU) 101, which is coupled to memory controller 102 byCPU bus 103. Embodiments having multiple processors are possible andcontemplated. Memory controller 102 is coupled to a plurality of memorymodules 1000 via memory bus 104. An error correction subsystem 104 maybe included in memory controller 102. Computer system 100 may alsoinclude a cache memory 109, which may be located within CPU 101 orexternal to CPU 101. Some embodiments may include both internal andexternal cache memories.

[0016] Computer system 100 also includes programmable read-only memory(PROM) 111 in the embodiment shown. PROM 111 may include instructionsthat, when executed by CPU 101, may perform various types of diagnostictesting. Such diagnostic testing may include memory tests, include thetests of memory devices located on memory modules 1000, memory bustests, and memory interconnect tests. In order to perform suchdiagnostic testing, the instructions located within PROM 111 may causethe generation of various bit patterns. These bit patterns may begenerated within certain constraints, such as routing constraintsresulting from the presence of error correction subsystem 105. Othermeans of generating the bit patterns (in lieu of the PROM) are possibleand contemplated for other embodiments. For example, in anotherembodiment the diagnostics may be an application run under the controlof an operating system. Generation and assignment of these bit patternswill be discussed in further detail below.

[0017] Moving now to FIG. 1B, a block diagram of one embodiment of amemory module is shown. Memory module 1000 may be a memory module usedin computer system 100 as discussed above. In the embodiment shown,memory module 1000 includes a plurality of memory devices 1001. Thesememory devices may be one of several different types of memory,including dynamic random access memory (DRAM). Memory devices 1001 maybe electrically connected to connector 1005, which may in turn couplememory module 1000 to a memory bus. Computer system 100 may include aplurality of memory modules 1000 which may be used to provide storagefor data and instructions during the execution of programs running onthe system.

[0018]FIG. 2 is a block diagram illustrating one embodiment of a cacheline and associated check words. The cache line may represent an amountof data that may be written or read from memory in one access. In theembodiment shown, cache line 200 is 4 check words (shown here as qwords,or quadwords) in width. For the purposes of this disclosure, the term“check word” includes both check bits and the data bits that areprotected by the check bits, and may include additional bits as well.For this particular embodiment, each check word includes a total of 144bits, although embodiments having larger or smaller check word sizes arepossible and contemplated. Similarly, cache lines having a greater orlesser number of check words are also possible and contemplated.

[0019] As noted above, each check word of the cache line in theembodiment shown includes 144 bits. Of these 144 bits, 128 bits are databits. Each check word also includes 9 bits of an error correction code(ECC). These 9 bits provide error protection for the 128 data bits. Eachcheck word may also include extra bits (such as the MTag and MTagECCbits) which are used for other purposes, or may be reserved for futureuse.

[0020] An error correction subsystem, such as error correction subsystem105 may read the data bits and ECC of check word 200 to determinewhether one or more data bits of the check word are in error. Varioustechniques may be used in order to determine the presence or absence ofa data error. In some embodiments, the ECC used is known as anSEC-DED-S4ED code—single error correcting, double error detecting, 4-bitnibble error detecting. In addition to detecting errors within aspecific check word, it is desirable to be able to detect errorsassociated with specific memory devices. Increasing the likelihood ofdetecting errors associated with specific memory devices placesadditional routing constraints on signal lines to and from each memorydevice. These constraints will now be illustrated below in reference toFIG. 3.

[0021]FIG. 3 is a block diagram illustrating the association of errorcorrection codes (ECCs) and memory devices. In the embodiment shown, twomemory devices 1001 are shown are providing bits to each of the checkwords 201 in cache line 200. In this particular example, memory devices1001 are 4 bits in width (i.e. 4 bits are read from the device in anygiven cycle). However, other embodiments are possible and contemplatedwherein a larger memory device (e.g., 16 bits in width) may be viewed asbeing subdivided into smaller devices, such as the 4-bit devices shown.

[0022] As shown in FIG. 3, each of the 4-bit memory devices provides abit to each of the 4 check words in cache line 200. Thus, in thisparticular case, no two bits from the same memory device 1001 arepresent in the same check word 201 of cache line 200. Thus, it ispossible that if one of memory devices 1001 completely fails, the errorcorrection subsystem may detect and correct 4 single-bit errors, one ineach check word. By identifying the bit location of each of the errors,it may be possible to identify the failing memory chip. This is onemethod of implementing a chip-kill correct DIMM. Chip-kill correctfunctionality may allow a memory system to recover from an event where asingle memory device fails.

[0023] It should be noted that, although 4-bit memory devices are shownhere, other embodiments are possible and contemplated using largerdevices, such as a 16-bit device which may be subdivided into four 4-bitdevices (in the case where the cache line has 4 check words). Specificdevice size and any subdivision size may be different for otherembodiments based on check word size (in bits) as well as the size ofthe cache line (in number of check words).

[0024] Due to the routing constraints that may exist in ensuring bitsfrom different devices (or subdivisions of a device) are assigned todifferent check words of a cache line, it may be necessary to ensurethat diagnostic patterns are generated such that the data bit patternswritten on a chip do not always write the same logic values to a givenmemory device. A method for achieving this goal is discussed in furtherdetail below in reference to FIG. 4.

[0025] Moving now to FIG. 4 is a block diagram illustrating variousmemory devices and potential subdivisions thereof. In the drawing shownhere, embodiments of three different memory devices are shown: 16-bitmemory 1001-A, 8-bit memories 1001-B and 4-bit memories 1001-C. The bitnumber for each of these memories is indicative of the number of bitsthat may be written or read during a memory cycle. Any of theembodiments shown may be used to read/write data in 16-bit blocks,although a combination of devices must be provided to achieve thisobjective for 8-bit memories 1001-B and 4-bit memories 1001-C.

[0026] Memory devices of larger sizes may be subdivided into smallersized memories for the purposes of performing error detection andcorrection, particularly in cases wherein the ECC is an SEC-DED-S4EDcode. Thus, 16-bit memory 1001-A may be viewed as four 4-bit memorydevices, where each of the 4-bit memory devices is associated with fourof the 16 bits of a 16-bit data block. Conversely, four 4-bit memorydevices 1001-C may be associated with single 16-bit data block as shown,and may thus be viewed as a single 16-bit memory device. In general,grouping bits of a data block into groups of 4 may make the memorysubsystem suitable for 4-bit nibble error detection (S4ED) by an errorcorrection subsystem. It should also be noted that memory device sizesand subdivision sizes other than those discussed here are possible andcontemplated.

[0027] It should be noted that embodiments are possible and contemplatedusing ECC subsystems having a different number of check bits, differenterror detection and correction codes, and different error detection andcorrection capabilities.

[0028] As noted above, bit assignments (i.e. assignment of various bitpositions of a data block) to check words of a cache line may beperformed such that each bit of the device is assigned to a differentcheck word of the cache line. Table 1 illustrates one such embodiment,wherein 16-bit memory devices are subdivided into groups of 4 bits, andwherein each bit of a 4-bit subdivision is assigned to a different checkword of the cache line. The left most column lists the signals for eachof the check words, while the remaining columns list the memory deviceand pin number to which those signals are routed to/from. For example,data bits 8, 9, 10, and 11 for check word 0 (QWord 0) is associated withmemory device D4, bits 14, 9, 4, and 3. For check word 1 of the cacheline, data bits 8, 9, 10, and 11 are associated with D4, bits 15, 8, 5,and 2. TABLE 1 signal (nibbles) QWord 0 QWord1 QWord2 QWord3MTagECC[0,1,2,3] D[0,1,2,3][0] D[0,1,2,3][1] D[0,1,2,3][2] D[0,1,2,3][3]MTag[0,1,2] D[0,1,2][7] D[0,1,2][6] D[0,1,2,][5] D[0,1,2][4] ECC[4]D[0][10] D[0][11] D[0][8] D[0][9] Data[0,1,2,3] D[3][7,10,13],D[1][10]D[3][6,11,12],D[1][11] D[3][5,8,15],D[1][8] D[3][4,9,14],D[1][9]Data[4,5,6,7] D[2][10],D[0,1,2][13] D[2][11],D[0,1,2][12]D[2][8],D[0,1,2][15] D[2][9],D[0,1,2][14] Data[8,9,10,11] D[4][14,9,4,3]D[4][15,8,5,2] D[4][12,11,6,1] D[4][13,10,7,0] Data[12,13,14,15]D[5][14,9,4,3] D[5][15,8,5,2] D[5][12,11,6,1] D[5][13,10,7,0]Data[16,17,18,19] D[6][14,9,4,3] D[6][15,8,5,2] D[6][12,11,6,1]D[6][13,10,7,0] Data[20,21,22,23] D[7][14,9,4,3] D[7][15,8,5,2]D[7][12,11,6,1] D[7][13,10,7,0] Data[24,25,26,27] D[8][0,7,10,13]D[8][1,6,11,12] D[8][2,5,8,15] D[8][3,4,9,14] Data[28,29,30,31]D[9][14,9,4,3] D[9][15,8,5,2] D[9][12,11,6,1] D[9][13,10,7,0]Data[32,33,34,35] D[10][14,9,4,3] D[10][15,8,5,2] D[10][12,11,6,1]D[10][13,10,7,0] Data[36,37,38,39] D[11][14,9,4,3] D[11][15,8,5,2]D[11][12,11,6,1] D[11][13,10,7,0] Data[40,41,42,43] D[12][14,9,4,3]D[12][15,8,5,2] D[12][12,11,6,1] D[12][13,10,7,0] Data[44,45,46,47]D]13][14,9,4,3] D[13][15,8,5,2] D[13][12,11,6,1] D[13][13,10,7,0]Data[48,49,50],ECC[2] D[14][14,9,4,3] D[14][15,8,5,2] D[14][12,11,6,1]D[14][13,10,7,0] Data[51,52,53],ECC[1] D[15][14,9,4,3] D[15][15,8,5,2]D[15][12,11,6,1] D[15][13,10,7,0] Data[54,55],ECC[3,0]] D[16][14,9,4,3]D[16][15,8,5,2] D[16][12,11,6,1] D[16][13,10,7,0] Data[56,57,58,59]D[17][14,9,4,3] D[17][15,8,5,2] D[17][12,11,6,1] D[17][13,10,7,0]Data[60,61,62,63] D[18][0,7,10,13] D[18][1,6,11,12] D[18][2,5,8,15]D[18][3,4,9,14] Data[64,65,66,67] D[19][0,7,10,13] D[19][1,6,11,12]D[19][2,5,8,15] D[19][3,4,9,14] Data[68,69,70,71] D[20][0,7,10,13]D[20][1,6,11,12] D[20][2,5,8,15] D[20][3,4,9,14] ECC[8,5],Data[72,73]D[21][14,9,4,3] D[21][15,8,5,2] D[21][12,11,6,1] D[21][13,10,7,0]ECC[7],Data[74,75,76] D[22][14,9,4,3] D[22][15,8,5,2] D[22][12,11,6,1]D[22][13,10,7,0] ECC[6],Data[77,78,79] D[23][14,9,4,3] D[23][15,8,5,2]D[23][12,11,6,1] D[23][13,10,7,0] Data[80,81,82,83] D[24][14,9,4,3]D[24][15,8,5,2] D[24][12,11,6,1] D[24][13,10,7,0] Data[84,85,86,87]D[25][14,9,4,3] D[25][15,8,5,2] D[25][12,11,6,1] D[25][13,10,7,0]Data[88,89,90,91] D[26][14,9,4,3] D[26][15,8,5,2] D[26][12,11,6,1]D[26][13,10,7,0] Data[92,93,94,95] D[27][14,9,4,3] D[27][15,8,5,2]D[27][12,11,6,1] D[27][13,10,7,0]

[0029] It should be noted that Table 1 is associated with an embodimentsimilar to the one described in FIG. 2, wherein each check word of thecache line is 144 bits wide. It should also be noted that Table 1 showsonly a portion of the bit assignments for each of 144-bit check words ofthe cache line. An alternate routing scheme is shown, in part, in Table2. TABLE 2 signal (nibbles) QWord 0 QWord1 QWord2 QWord3MTagECC[0,1,2,3] D[0,1,2,3][14] D[0,1,2,3][15] D[0,1,2,3][12]D[0,1,2,3][13] MTag[0,1,2] D[0,1,2][9] D[0,1,2][8] D[0,1,2][11]D[0,1,2][10] ECC[4] D[0][4] D[0][5] D[0][6] D[0][7] Data[0,1,2,3]D[3][9,4,3],D[1][4] D[3][8,5,2],D[1][5] D[3][11,6,1]D[1][6]D[3][10,7,0],D[1][7] Data[4,5,6,7] D[2][4],D[0,1,2][3]D[2][5],D[0,1,2][2] D[2][6],D[0,1,2][1] D[2][7],D[0,1,2][0]Data[8,9,10,11] D[4][0,7,10,13] D[4][1,6,11,12] D[4][2,5,8,15]D[4][3,4,9,14] Data[12,13,14,15] D[5][0,7,10,13] D[5][1,6,11,12]D[5][2,5,8,15] D[5][3,4,9,14] Data[16,17,18,19] D[6][0,7,10,13]D[6][1,6,11,12] D[6][2,5,8,15] D[6][3,4,9,14] Data[20,21,22,23]D[7][0,7,10,13] D[7][1,6,11,12] D[7][2,5,8,15] D[7][3,4,9,14]Data[24,25,26,27] D[8][14,9,4,3] D[8][15,8,5,2] D[8][12,11,6,1]D[8][13,10,7,0] Data[28,29,30,31] D[9][0,7,10,13] D[9][1,6,11,12]D[9][2,5,8,15] D[9][3,4,9,14] Data[32,33,34,35] D[10][0,7,10,13]D[10][1,6,11,12] D[10][2,5,8,15] D[10][3,4,9,14] Data[36,37,38,39]D[11][0,7,10,13] D[11][1,6,11,12] D[11][2,5,8,15] D[11][3,4,9,14]Data[40,41,42,43] D[12][0,7,10,13] D[12][1,6,11,12] D[12][2,5,8,15]D[12][3,4,9,14]

[0030] For the embodiment of Table 2, data bits 8, 9, 10, and 11 ofcheck word 0 may be associated with memory device D4, bits 0, 7, 10, and13, data bits 8, 9, 10, and 11 of check word 1 may be associated withD4, bits 1, 6, 11, and 12, and so on.

[0031] As the difference between Table 1 and Table 2 demonstrates,routing of bits of system memory devices to check words in a cache linemay vary from platform to platform. Furthermore, the routing of bitsfrom memory devices to check words in a cache line may vary within thesame platform. For example, Table 1 shown above may represent therouting assignments for a first side of a DIMM (dual inline memorymodule) while Table 2 may represent the routing for the second side ofthe DIMM.

[0032] Since the routing assignments may change from platform toplatform, and may even vary on a given platform, it may be necessary toensure that bit patterns generated for diagnostic tests are generated insuch a manner that each device/subdivision will see all relevant bitpatterns.

[0033] One embodiment of a method for generating bit patterns such thateach device/subdivision will see all of the relevant bit patternsincludes generating 2^(m) bit patterns, wherein m is the number of bitsof each device/subdivision. For example, m=4 for the embodimentsassociated with Tables 1 and 2 shown above, since the size of each ofthe subdivisions is 4 bits. In cases where the memory device is larger(in width) than the bit-width of each of the groupings, the memorydevice may be subdivided into n subdivisions. For the embodimentdescribed herein, n=4 for a 16-bit memory device divided into 4subdivisions of 4 bits each. However, it should be noted thatembodiments having different values for m and n are possible andcontemplated.

[0034] In one embodiment, the number of subdivisions of a memory devicemay be equal to the number of check words in the cache line. Such is thecase in this embodiment, wherein the cache line includes 4 check words,and wherein each 16-bit memory device includes four 4-bit subdivisions.In other embodiments, the number of check words in the cache line maynot necessarily be equal to the number of subdivisions of each memorydevice.

[0035] In some embodiments, the memory devices may not be subdivided. Insuch cases, while n may indicate the number of check words in the cacheline, it is not applicable to the memory devices since there are nosubdivisions.

[0036] In embodiments where subdivisions of a memory device areperformed, the subdivisions are performed according to significance ofthe bits in each grouping. For example, in a 16-bit device, the firstsubdivision may include bits 0-3, while the second subdivision includesbits 4-7, the third subdivision includes bits 8-11, and the fourthsubdivision includes bits 12-15. Each bit of a given subdivision may beassigned to a different check word of the cache line with respect toeach of the other bits of the subdivision.

[0037] Once a bit pattern has been generated bits may be assigned toboth a memory device/subdivision and to each check word in the cacheline. Each of the m bits of a memory device subdivision may be assignedto a different check word of the cache line, so that no check wordincludes more than one bit from that particular subdivision. In the casewhere memory devices are not subdivided, the assignments of each of them bits of the device may ensure that no check word in the cache line isassociated more than one bit of that device. In the example shownherein, since m=4 and n=4, one bit from each subdivision may be assignedto each check word of the cache line.

[0038] The bit patterns generated for one embodiment are shown below inTable 3. Other embodiments are possible and contemplated, and may varyin both the size and number of bit patterns based on factors such as thenumber of check words in the cache line. These bit patterns are assignedto the check words of the cache line. Thus, the assignment of bitpatterns to each memory device may vary depending on the platform. Forexample, while the bit assignments to specific memory devices may bedifferent for the routing scheme illustrated in Table 1 with respect tothe routing scheme illustrated in Table 2. However, either of theembodiments illustrated in FIGS. 1 and 2 may utilize the bit patternsillustrated in Table 3.

[0039] The bit patterns shown in the embodiment of Table 3 include 2^(m)(where m=4 and 2^(m)=16 in this case) basic bit patterns. Individualbits of the basic bit pattern may be repeated in their assignment toeach of the check words of the cache line. For example, where the basicbit pattern is 0011, logic 0's are assigned to all bit positions incheck words 0 and 1, while logic 1's are assigned to all bit positionsin check words 2 and 3.

[0040] Similarly, if the basic bit pattern is 1001, logic 0's areassigned to all bit positions in 1 and 2, while logic 1's are assignedto all bit positions in check words 0 and 3. TABLE 3 Basic Check CheckCheck Check Patterns word 0 word 1 word 2 word 3 0000 All 0's All 0'sAll 0's All 0's 0001 All 0's All 0's All 0's All 1's 0010 All 0's All0's All 1's All 0's 0011 All 0's All 0's All 1's All 1's 0100 All 0'sAll 1's All 0's All 0's 0101 All 0's All 1's All 0's All 1's 0110 All0's All 1's All 1's All 0's 0111 All 0's All 1's All 1's All 1's 1000All 1's All 0's All 0's All 0's 1001 All 1's All 0's All 0's All 1's1010 All 1's All 0's All 1's All 0's 1011 All 1's All 0's All 1's All1's 1100 All 1's All 1's All 0's All 0's 1101 All 1's All 1's All 0'sAll 1's 1110 All 1's All 1's All 1's All 0's 1111 All 1's All 1's All1's All 1's

[0041] For the embodiments discussed above, each 4-bit memory device or4-bit subdivision may be associated with one bit to each check word ofthe cache line. Thus, while each check word in the cache line may becomprised of all logic 0's or all logic 1's according to the generatedbit patterns, each device may be associated with logic 0's and logic1's. For example, for the bit pattern 0011, a given device may providetwo logic 0's and two logic 1's.

[0042] Table 4 below illustrates the association of patterns with deviceD4 according to the routing assignments of Table 1. In this particularembodiment, each group of four bit positions (0-3, 4-7, 8-11, and 12-15)provides a single bit to each of the four check words of the cache line.For example, taking the group of bit positions 12-15, 12 is associatedwith check word 2, 13 is associated with check word 3, 14 is associatedwith check word 0, and 15 is associated with check word 1. TABLE 4Patterns associated with Device D4 according to the routing assignmentsof Table 1 Bit #'s 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Basic W W W W WW W W W W W W W W W W Patterns 1 0 3 2 2 3 0 1 3 2 1 0 0 1 2 3 0000 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0001 0 0 1 0 0 1 0 0 1 0 0 0 0 0 0 1 0010 00 0 1 1 0 0 0 0 1 0 0 0 0 1 0 0011 0 0 1 1 1 1 0 0 1 1 0 0 0 0 1 1 01001 0 0 0 0 0 0 1 0 0 1 0 0 1 0 0 0101 1 0 1 0 0 1 0 1 1 0 1 0 0 1 0 10110 1 0 0 1 1 0 0 1 0 1 1 0 0 1 1 0 0111 1 0 1 1 1 1 0 1 1 1 1 0 0 1 11 1000 0 1 0 0 0 0 1 0 0 0 0 1 1 0 0 0 1001 0 1 1 0 0 1 1 0 1 0 0 1 1 00 1 1010 0 1 0 1 1 0 1 0 0 1 0 1 1 0 1 0 1011 0 1 1 1 1 1 1 0 1 1 0 1 10 1 1 1100 1 1 0 0 0 0 1 1 0 0 1 1 1 1 0 0 1101 1 1 1 0 0 1 1 1 1 0 1 11 1 0 1 1110 1 1 0 1 1 0 1 1 0 1 1 1 1 1 1 0 1111 1 1 1 1 1 1 1 1 1 1 11 1 1 1 1

[0043] For a large check word size (e.g., the 144-bit check wordsdiscussed above), a plurality of memory devices may be used to form thecheck words. However, since the devices or subdivisions may be smallrelative to the check word size, a relatively small number of bitpatterns need be generated in order to perform an effective diagnostictest. In the embodiments discussed above, with four 144-bit check wordsin the cache line (and thus 576 bits total in the cache line) using4-bit memory devices or 4-bit subdivisions may allow an effectivediagnostic testing routine having a total of only 16 bit patterns. Thismay minimize the necessary testing time while ensuring that each bitposition is toggled between a logic 0 and a logic 1 enough times toverify functionality (or the presence of an error). Generating bits inaccordance with an embodiment of the method illustrated by Table 3 maybe generic, i.e. it may be applied to various platforms with differentrouting schemes, such as the alternate scheme illustrated in Table 2,while ensuring that each bit position is toggled between a logic 0 and alogic 1 several times.

[0044] While the present invention has been described with reference toparticular embodiments, it will be understood that the embodiments areillustrative and that the invention scope is not so limited. Anyvariations, modifications, additions, and improvements to theembodiments described are possible. These variations, modifications,additions, and improvements may fall within the scope of the inventionsas detailed within the following claims.

What is claimed is:
 1. A method for generating bits of a diagnosticroutine to a memory subsystem, the method comprising: subdividing amemory device into n subdivisions, wherein each of the n subdivisionincludes m bits; generating one of 2^(m) bit patterns; and assigning mbits of the one of the 2^(m) bit patterns to a check word in a cacheline, wherein each of the m bits assigned to the check word in the cacheline have the same logic value, and wherein each bit of one of the nsubdivisions is associated with a different check word in the cache linewith respect to other bits of the one of the n subdivisions.
 2. Themethod as recited in claim 1, wherein each of the m bits of the checkword in the cache line is associated with a different memory device. 3.The method as recited in claim 1, wherein at least one of the bitpatterns assigned to one of the n subdivisions matches the one of the2^(m) bit patterns.
 4. The method as recited in claim 1 furthercomprising cycling through each of the 2^(m) bit patterns.
 5. The methodas recited in claim 1, wherein the cache line includes a plurality ofcheck words, and wherein each of the plurality of check words isassociated with one of the m bits of each of the n subdivisions.
 6. Themethod as recited in claim 5, wherein n=4.
 7. The method as recited inclaim 5, wherein m=4.
 8. The method as recited in claim 7, wherein thememory device is 16 bits wide.
 9. The method as recited in claim 5,wherein each of the plurality of check words includes 144 bits.
 10. Themethod as recited in claim 1, wherein the memory device is a randomaccess memory (RAM).
 11. The method as recited in claim 9, wherein thememory device is a dynamic RAM (DRAM).
 12. A computer system including amemory subsystem, the computer system comprising: a memory controller; acache memory coupled to the memory controller, wherein the cache memoryis associated with a cache line having a plurality check words; and aplurality of memory devices coupled to the memory controller by a memorybus; wherein the computer system is configured to generate bit patternsfor performing a diagnostic routine on the memory subsystem, saidgenerating including: subdividing each of the plurality of memorydevices into n subdivisions, wherein each of the n subdivisions includesm bits; generating one of 2^(m) bit patterns; and assigning m bits ofone of the 2^(m) bit patterns to one of the plurality of check words inthe cache line, wherein each of the m bits assigned to the one of theplurality of check words in the cache line have the same logic value,and wherein each bit of one of the n subdivisions is associated with adifferent one of the plurality of check words in the cache line withrespect to other bits of the one of the n subdivisions.
 13. The computersystem as recited in claim 12, wherein each of the m bits of theassociated check word in the cache line is received from a differentmemory device.
 14. The computer system as recited in claim 12, whereinfor at least one of the a bit pattern assigned to one of the nsubdivisions matches the one of the 2^(m) bit patterns.
 15. The computersystem as recited in claim 12, wherein the cache is an external cache.16. The computer system as recited in claim 12, wherein the cache islocated in a processor, wherein the processor is coupled to the memorycontroller by a CPU bus.
 17. The computer system as recited in claim 1,wherein n=4.
 18. The computer system as recited in claim 17, whereinm=4.
 19. The computer system as recited in claim 18, wherein each of theplurality of memory devices is 16 bits wide.
 20. The computer system asrecited in claim 17, wherein each of the plurality of check wordsincludes 144 bits.
 21. The computer system as recited in claim 12,wherein the memory controller includes an error correction subsystem.22. The computer system as recited in claim 12, wherein each of theplurality of memory devices is a random access memory (RAM).
 23. Thecomputer system as recited in claim 22, wherein each of the plurality ofmemory devices is a dynamic RAM (DRAM).
 24. A method of generating bitsof a diagnostic pattern to a memory subsystem, the method comprising:generating one of 2^(m) bit patterns; and assigning m bits of one of the2^(m) bit patterns to one of a plurality of check words in a cache line,and wherein each of the plurality of check words of the cache line isassociated with one bit of a memory device m bits wide; wherein each ofthe m bits assigned to the check word in the cache line have the samelogic value, and wherein each of the m bits of the memory device isassociated with a different one of the plurality of check words in thecache line with respect to other ones of the m bits of the memorydevice.
 25. The method as recited in claim 24, wherein n=4.
 26. Themethod as recited in claim 24, wherein m=4.
 27. The method as recited inclaim 24, wherein the memory device is a dynamic random access memory(DRAM).
 28. A computer system comprising: a memory controller; a cachememory coupled to the memory controller, wherein the cache memory isassociated with a cache line having a plurality of check words; and aplurality of memory devices coupled to the memory controller by a memorybus, wherein each of the memory devices is m bits wide; wherein thecomputer system is configured to generate bit patterns for a diagnosticroutine, said generating including: generating one of 2^(m) bitpatterns; and assigning m bits of one of the 2^(m) bit patterns to oneof the plurality of check words in the cache line, wherein each of theplurality of check words of the cache line is associated with one bit ofeach of the plurality of memory devices; wherein each of the m bitsassigned to the one of the plurality of check words in the cache linehave the same logic value, and wherein each of the m bits of the memorydevice is associated with a different one of the plurality of checkwords in the cache line with respect to other ones of the m bits of thememory device.
 29. The computer system as recited in claim 28, whereinm=4.
 30. The computer system as recited in claim 28, wherein n=4. 31.The computer system as recited in claim 28, wherein each of theplurality of memory devices is a dynamic random access memory (DRAM).